The present invention relates to an impedance adjusting circuit used in various integrated circuits such as a semiconductor memory device, and more particularly, to an impedance adjusting circuit configured to easily measure an offset value.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most semiconductor devices include a receiving circuit configured to receive signals from an outside world via input pads and an output circuit configured to provide internal signals to an outside world via output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on an external noise, causing the signal reflectance to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion in output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in decision of an input level.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance adjusting circuit near an input pad inside an IC chip. In a typical impedance adjusting circuit scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to a receiving circuit coupled to the input pad.
A ZQ calibration refers to a procedure of generating pull-up and pull-down codes which are varied with PVT (process, voltage and temperature) conditions. The resistance of the impedance adjusting circuit, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the codes resulting from the ZQ calibration. Here, the term of ZQ calibration is attributed to the fact that the calibration is performed using a ZQ node.
Hereinafter, how the ZQ calibration is performed in an impedance adjusting circuit will be described.
FIG. 1 is a block diagram of a calibration circuit for performing a ZQ calibration in a conventional impedance adjusting circuit.
Referring to FIG. 1, the conventional impedance adjusting circuit configured to perform ZQ calibration includes a first calibration resistor circuit 110, a second calibration resistor circuit 120 and 130, a reference voltage generator 102, first and second comparators 103 and 104, and pull-up and pull-down counters 105 and 106. The first calibration resistor circuit 110 is provided with a plurality of pull-up resistors which are turned on/off in response to a pull-up calibration code PCODE<0:N>. The second calibration resistor circuit 120 and 130 includes a pull-up calibration resistor unit 120 and a pull-down calibration resistor unit 130. Here, the pull-up calibration resistor unit 120 has the same construction as the first calibration resistor circuit 110. The pull-down calibration resistor unit 130 is provided with a plurality of pull-down resistors which are turned on/off in response to a pull-down calibration code NCODE<0:N>.
The first calibration resistor circuit 110 generates the pull-up calibration code PCODE<0:N> primarily while being calibrated with an external resistor 101 connected to a ZQ node. The second calibration resistor circuit 120 and 130 generates the pull-down calibration code NCODE<0:N> secondarily using the pull-up calibration code PCODE<0:N> which has been generated through the first calibration resistor circuit 110.
The first comparator 103 compares a ZQ node voltage at the ZQ node with a reference voltage VREF (generally, set to VDDQ/2) generated from the reference voltage generator 102, thereby generating up/down signals UP/DOWN. Herein, the ZQ node voltage is generated by coupling the first calibration resistor circuit 110 to the external resistor 101 (generally, 240 Ω) connected to a ZQ pin that is disposed outside a chip of the ZQ node.
The pull-up counter 105 receives the up/down signals UP/DOWN to generate the pull-up calibration code PCODE<0:N> as a binary code, which turns on/off the pull-up resistors connected in parallel in the first calibration resistor circuit 110, thereby calibrating total resistance of the first calibration resistor circuit 110. The calibrated resistance of the first calibration resistor circuit 110 affects the ZQ node voltage again, and the above-described calibration procedure is then repeated. That is, the first calibration resistor circuit 110 is calibrated such that the total resistance of the first calibration resistor circuit 110 is equal to the resistance of the external resistor 101, which is called a pull-up calibration.
The binary code, i.e., the pull-up calibration code PCODE<0:N>, generated during the pull-up calibration is inputted into the pull-up calibration resistor unit 120 of the second calibration resistor circuit 120 and 130, thereby determining total resistance of the pull-up calibration resistor unit 120. Thereafter, a pull-down calibration starts to be performed in a similar manner to the pull-up calibration. Specifically, the pull-down calibration is performed such that a voltage of a node A is equal to the reference voltage VREF using the second comparator 104 and the pull-down counter 106, that is, the total resistance of the pull-down calibration resistor unit 130 is equal to the total resistance of the pull-up calibration resistor unit 120.
The binary codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration, i.e., pull-up and pull-down calibrations, are inputted to pull-up and pull-down resistors (termination resistors) at input/output pads, which are identically configured to the pull-up and pull-down calibration resistor units in the calibration resistor circuit of FIG. 1, thus determining resistance of the impedance adjusting circuit. In a memory device, resistances of pull-up and pull-down resistors at a DQ pad are determined.
For reference, although both pull-up and pull-down calibration operations are performed to generate the pull-up calibration codes PCODE<0:N> and the pull-down calibration codes NCODE<0:N> for determining resistances of the pull-up and pull-down calibration resistor units of the conventional impedance adjusting circuit, the impedance adjusting circuit needs not necessarily include both the pull-up and pull-down termination resistor circuits in the impedance adjusting circuit. For example, both the pull-up and pull-down resistor circuits are used at a side of an output driver in the case of a semiconductor memory device, but only the pull-up termination resistor circuit is used at a side of an input buffer.
Therefore, if the impedance adjusting circuit includes only the pull-up termination resistor circuit at input/output pads, the calibration resistor circuit of FIG. 1 only includes the pull-up calibration resistor circuit 110, the pull-up counter 105 and the first comparator 103, which are configured to generate the pull-up calibration codes PCODE<0:N>. An operation of this case is the same as the above-described pull-up calibration.
FIG. 2 is a block diagram illustrating how termination resistance of an output driver of a semiconductor memory device is determined using the calibration codes PCODE<0:N> and NCODE<0:N> generated from the calibration circuit of FIG. 1.
The output driver configured to output data in the semiconductor memory device includes first and second pre-drivers 210 and 220 located at its upper and lower parts, and pull-up and pull-down termination resistor units 230 and 240 for outputting data.
The first and second pre-drivers 210 and 220 control the pull-up termination resistor unit 230 and the pull-down resistor unit 240, respectively. When outputting a data having a logic high level, the pull-up termination resistor unit 230 is turned on so that a data pin DQ goes to ‘HIGH’ state. On the contrary, when outputting a data having a logic low level, the pull-down termination resistor unit 240 is turned on so that the data pin DQ goes to ‘LOW’ state. That is, the data pin DQ is pull-up or pull-down terminated to thereby output a data of a logic high level or a logic low level.
At this time, the number of resistors in the pull-up and pull-down termination resistors 230 and 240 to be turned on is determined by the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N>. Specifically, which resistor unit is turned on between the pull-up and pull-down termination resistor units 230 and 230 is mainly determined depending on a logic level of output data, but which resistor is turned on among the termination resistors provided in one of the termination resistor units 230 and 240 that has been selected to be turned on is determined by the pull-up calibration code PCODE<0:N> or pull-down calibration code NCODE<0:N>.
For reference, target resistances of the pull-up and pull-down resistor units 230 and 240 are not necessarily equal to resistances (240 Ω) of the first and second resistor circuits (see “110”, “120” and “130” of FIG. 1) but may have a resistance of one-half (120 Ω) or one-quarter (60 Ω) of 240 Ω, etc. In FIG. 2, reference symbols “DQP_CTRL” and “DQN_CTRL” inputted to the first and second pre-drivers 210 and 220 denote various control signals exemplarily.
The ZQ calibration operation of the conventional impedance adjusting circuit is based on the assumption that there is no mismatch between the calibration resistors (110, 120 and 130 of FIG. 1) and the termination resistors 230 and 240 and the resistance can be increased or decreased at a predetermined ratio.
However, mismatch exists between the resistors due to process variation or the like. Hence, the termination resistor may not have a target resistance due to several factors such as an offset of a comparator in the calibration circuit, a noise in a power supply voltage, a line loading, pad resistance and package resistance.
In the conventional impedance adjusting circuit, the ZQ calibration can be verified only by specifying resistance of the termination resistor. That is, the termination resistance can be measured by directly connecting a DQ pin to the termination resistor but there is no way to measure the resistance of the calibration resistor. In particular, it is difficult to measure an internal voltage level after being packaged, which may lead to more serious problems.
That is, the conventional impedance adjusting circuit has a problem in that it is not easy to find out which portion of the impedance adjusting circuit gives rise to a trouble when the ZQ calibration does not normally operate.